In order to reduce power consumption of modern Integrated Circuits (ICs), many ICs now include the ability to turn off unused portions of the IC. However, to ensure the respective portion(s) of the IC are able to quickly return to their fully operational state, particularly the exact logical state the portion(s) of the IC were in prior to them being powered down, certain state parameters are stored in a local memory. These stored state parameters are then loaded back into the IC portion(s), immediately after those portion(s) have been powered up again, so that the respective portion(s) of the IC may carry on from where they were before. A form of this process is often referred to as State Retention Power Gating.
The State Retention Power Gating (SRPG) technique is still one of the most aggressive power management techniques, because it allows the gating (i.e. turning off) of the power supply to the respective portion(s) of the IC, and thus saves power wastage/loss through leakage currents and the like, whilst still enabling the IC portion to get back into its previous logical state.
Leakage currents (e.g. the leakage within the well of a transistor) are increasing, as the dimensions of the transistors, and the like, that form ICs get smaller with each iteration of the semiconductor manufacturing process.
Originally, SRPG was intended to be implemented using specially provided Flip Flop (FF) circuitry (i.e. retention latches), so that the state data may be stored local to the respective logic circuit. However, as ICs increased in size, hence requiring increasing amounts of local FF to be provided in an IC, it became less and less efficient to store state data these in retention latches. Thus, it became prevalent to save the state data in a more centralised dedicated SRPG memory, by moving the state data through the scan chains (i.e. test portions of the ICs under test) and out for storage in the centralised SRPG memory.